1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the device. More particularly, the present invention relates to a HEMT (High Electron Mobility Transistor) which intends to reduce a gate leakage current.
2. Description of Related Art
FIG. 6 is a plan view showing one example of a semiconductor device having a HEMT structure. FIG. 7 is a cross-sectional view taken along a line VII-VII′ in FIG. 6. As shown in FIGS. 6 and 7, the semiconductor device has a structure consisting of a semi-insulating substrate 1, a buffer layer 2, a channel layer 3, a spacer layer 4, an electron supplying layer 5 and a barrier layer 6, which are sequentially deposited onto the semi-insulting substrate 1 by using an epitaxial growth method (see FIG. 7). Thus, an operating region 11 can be formed as an element of the HEMT.
As shown in FIG. 6, three electrodes, namely, a source electrode 7, a gate electrode 8, and a drain electrode 9, are disposed on the barrier layer 6. The gate electrode 8 is provided so that a Schottky contact is established between the gate electrode 8 and the barrier layer 6. Further, the source electrode (pad) 7 and the drain electrode (pad) 9 are provided so that an Ohmic contact is established with respect to the channel layer 3.
The channel layer 3 is made of an InGaAs layer having no impurity doped thereinto (i.e., highly purified material) The electron supplying layer 5 is made of an n-type InAlAs layer doped with Si as an impurity, for example.
The semiconductor device (HEMT) constructed as described above has an electron affinity larger at the channel layer 3 than at the electron supplying layer 5. Therefore, electrons released from impurity atoms doped into the electron supplying layer 5 will be moved to the channel layer 3 and intensively concentrated in two dimensions at the surface of the channel layer 3. Since the channel layer 3 is made of a highly purified crystalline material containing no impurity, and hence there is little dispersion due to the impurity, the electrons concentrated at the surface of the channel layer 3 can move through the surface thereof with a high electron mobility. Furthermore, since the electron density also is high, a transistor operating at a high speed can be realized.
The barrier layer 6 is made of a non-doped InAlAs layer. Owing to the presence of the barrier layer 6, electrons can be prevented from moving between the operating region 11 and the gate electrode 8, so that a gate leakage current can be suppressed.
The spacer layer 4 is made of a non-doped InAlAs layer. Owing to the presence of the spacer layer 4, the channel layer 3 can be protected from an electric influence from impurity ions that have released electrons. Thus, electrons can be moved through the channel layer 3 without the influence. The buffer layer 2 also is made of a non-doped InAlAs layer. Owing to the presence of the buffer layer 2, the channel layer 3 can be protected from an influence from a crystalline defect of the semi-insulating substrate 1 made of InP. If the semi-insulating substrate 1 is made of a material having a satisfactory crystalline nature, the buffer layer 2 is not always necessary.
In general, a semiconductor device, as a method for electrically insulated separation of adjacent elements, there is employed a method in which ions such as B+, O+ are implanted to create a high resistivity region between the semiconductor elements requested to be insulated from each other. However, if the semiconductor device has a structure in which the non-doped InGaAs layer (channel layer 3) and the n-type InAlAs layer (electron supplying layer 5) are epitaxially grown on the semi-insulating substrate 1 as described above, ion implantation to form the high resistivity region is impossible. Therefore, if the HEMT has the above-described structure, a so-called mesa isolation method is introduced. That is, a wet etching is effected on the semiconductor device to remove unnecessary portions so that the operating regions 11 can be made into an island structure in which elements are separated and electrically isolated from one another.
The gate electrode 8 is formed so as to extend from an upper surface of the operating region 11, which is separated from other components on the substrate as an island structure by means of a mesa isolation method, to a periphery side of the operating region 11 so as to cover a side wall 12a thereof. This method is employed to respond to the following two requests: a high accuracy in mask alignment at the time when a gate electrode is formed on the device, and controllability of a drain current over the wider area of the operating region 11 owing to the electric field effect of the gate electrode 8. Meanwhile, the other end side of the gate electrode 8 is similarly extended toward the outside of the operating region 11 and connected to a gate leading portion (or a pad portion).
However, in the semiconductor device having the above-described structure, the gate electrode 8 will be brought into contact with the non-doped InGaAs layer (channel layer 3) and the n-type InAlAs layer (the electron supplying layer 5) at the side wall portion 12a of the operating region 11. Furthermore, the materials of InGaAs and n-type InAlAs essentially have a narrow band gap, and a Schottky barrier thereof with respect to a gate electrode made of a metal is low. Therefore, there is a problem in which movement of the electrons between the channel layer 3 or the electron supplying layers and the gate electrode 8, that is, a gate leakage current, is increased so that HEMT performance is deteriorated.
FIG. 8 shows a conventional arrangement for avoiding the above-described problems. As shown in FIG. 8, the operating region 11 is patterned into an island structure to be mesa isolated. Thereafter, the non-doped InGaAs layer (the channel layer 3) is selectively etched with respect to other layers made of InAlAs so that the side wall portions of the channel layer 3 are recessed. Subsequently, the gate electrode 8 is formed. In this way, a space a is provided between the gate electrode 8 and the channel layer 3. According to the above-mentioned method, however, the selective etching ratio of the InGaAs layer relative to the InAlAs layer is not satisfactory. Furthermore, it is unavoidable for the gate electrode 8 to be contacted to the n-type InAlAs layer (the electron supplying layers). Therefore, an effect of reducing the aforementioned gate leakage current is not obtained satisfactorily.
FIG. 9 is a diagram for explaining a method in which the gate electrode 8 can be prevented from being contacted to a side wall 12b. As shown in FIG. 9, when the operating region 11 is patterned into an island structure to be mesa isolated, the gate electrode 8 is prevented from contacting the side wall 12b by making the side wall 12b into an inverted-taper shape. In this case, however, the operating region 11 cannot have the benefit of satisfactory step coverage at an upper corner thereof, and the gate electrode 8 will suffer from cut up there. Further, when the operating region 11 undergoes the patterning process, the gate electrode extending direction, is limited depending on the crystal orientation of the side wall 12b i.e., a pattern layout is limited because of the inverted-taper shape at the side wall 12b. 